1. Field of the Invention
The present invention relates to a phase shifter, and more particularly, to a phase shifter that shifts a phase of a signal waveform based on switching between filters having different characteristics.
2. Description of Related Art
In general, phase shifters are necessary for communications using phased array technology and the like. Each phase shifter for shifting the phase of an input signal is required to have a high phase shift accuracy to shift the phase of the input signal. In order to achieve the high phase shift accuracy during normal use, it is necessary to reduce an input/output reflection coefficient (i.e., to improve an input/output return loss). Note that the phase shifter is also required to have a smaller passage loss.
As an example of the phase shifter using a field-effect transistor (hereinafter referred to as “FET”), switching phase shifters for obtaining a phase difference by using a switch (hereinafter also abbreviated as “SW”) to switch between a high-pass filter (HPF) and a low-pass filter (LPF) are widely employed.
“The phase shifters of this type have a problem of a great loss in the SW unit. In view of this, an embedded phase shifter for shifting a phase without using the SW has been studied and proposed in order to reduce the loss (see Japanese Unexamined Utility Model Application Publication No. 07-33026 (hereinafter referred to as “Patent Document 1”), U.S. Pat. No. 4,963,773 (hereinafter referred to as “Patent Document 2”), Japanese Unexamined Patent Application Publication No. 2001-339276(hereinafter referred to as “Patent Document 3”), Japanese Unexamined Patent Application Publication No. 2001-326558 (hereinafter referred to as “Patent Document 4”), Japanese Unexamined Patent Application Publication No. 08-213868 (hereinafter referred to as “Patent Document 5”), “IEEE TRANSACTION ON MICROWAVE THEORY AND TECHNIQUES”, p. 2652, Vol. 48, No. 12, Dec. 2000 (hereinafter referred to as “Non-patent Document 1”), and “Microwave and Millimeter Wave Phase Shifters”, Volume II, p. 411 (hereinafter referred to as “Non-patent Document 2”)).”
The phase shifter disclosed in Patent Document 1 switches the gate voltages of FETs, which allows the circuit itself to switch between the LPF and the HPF. The phase shifter switches between the HPF and the LPF, thereby shifting the phase of the input signal.
Patent Document 2 also discloses a phase shifter that switches the gate voltages of FETs, which allows the circuit itself to switch between the LPF and the HPF.
Referring now to FIGS. 10 11, 12A, 12B, 12C, 13A, 13B, and 13C, the phase shifter disclosed in Non-patent Document 1 will be described.
As shown in FIG. 10, a phase shifter 50 includes inductors 4a and 4b, an FET 5, a capacitor 6, an FET 7, and an inductor 8.
The inductors 4a and 4b are sequentially connected in series between an input terminal 1 and an output terminal 2. The FET 5 forms a bypass between the inductors 4a and 4b. The capacitor 6 is connected between the drain and source of the FET 5. The FET 7 is connected between a node between the inductors 4a and 4b and a ground. The inductor 8 is connected between the drain and source of the FET 7.
The control terminals of the FETs 5 and 7 receive complementary control voltages from the respective terminals 17a and 17b, and the FETs 5 and 7 operate complementarily. Specifically, when the FET 5 is in an on-state, the FET 7 is in an off-state. When the FET 7 is in the on-state, the FET 5 is in the off-state.
Note that the impedance of the FET which is in the on-state is equivalent to a small resistance, and the impedance of the FET which is in the off-state is equivalent to a small capacitance. Specifically, as shown in FIG. 11, the FET 5 which is in the on-state can be replaced with a small resistance 9, and the FET 5 which is in the off-state can be replaced with an OFF capacitance 10. Likewise, the FET 7 which is in the on-state can be replaced with a small resistance 11, and the FET 7 which is in the off-state can be replaced with an OFF capacitance 12.
Consideration is first given to the case where the FET 5 is in the on-state and the FET 7 is in the off-state. The phase shifter 50 shown in FIG. 10 can be depicted as FIG. 12A. Please note that in each drawing, the same numerals are given to the same components.
Assuming that the inductance of the inductor 8 is represented by L3 and the capacitance value of the OFF capacitance 12 is represented by Coff2, when the inductance L3 is set so as to satisfy the condition ω2L3Coff 2 =1, the inductor 8 and the FET 7 are in parallel resonance. Accordingly, the phase shifter shown in FIG. 12A can be depicted as FIG. 12B. Since the resistance 9 is a small resistance, the input/output terminals 1/2 are substantially short-circuited. As a result, the circuit shown in FIG. 12B can be replaced with the circuit shown in FIG. 12C.
Next, consideration is given to the case where the FET 5 is in the off-state and the FET 7 is in the on-state. The phase shifter shown in FIG. 10 can be depicted as FIG. 13A.
Since the resistance 11 is a small resistance, the phase shifter shown in FIG. 13A can be depicted as FIG. 13B. Further, assuming that the composite capacitance of the OFF capacitance 10 and the capacitor 6 corresponds to a capacitance 13, the phase shifter shown in FIG. 13B can be depicted as FIG. 13C.
Assuming that the inductance of the inductor 4a is represented by L2a; the inductance of the inductor 4b is represented by L2b; and the capacitance of the composite capacitance 13 is represented by Ct, each constant is set so as to satisfy L2a=L2b, Bn=2Xn/(1+Xn2)[where Bn represents an admittance due to the L2a, and Xn represents an impedance due to. As a result, the circuit shown in FIG. 13C functions as the HPF matched with a characteristic impedance. The phase of an output signal of the phase shifter shown in FIG. 13C advances by Φ=2arctan (ωL2a) relative to the phase of an output signal of the phase shifter shown in FIG. 12C (see Non-patent Document 2). Thus, it is possible to configure the phase shifter capable of switching the passing phase by alternately switching the gate biases of the FETs 5 and 7.
Each of the inductors 4a and 4b is generally formed by a line which has a spiral structure or the like and formed on a semiconductor substrate, i.e., a distributed constant circuit.
As described above, the phase shifter shown in FIG. 12B can be depicted as FIG. 12C. However, the present inventor studied and revealed that a line 14 constituting the inductors 4a and 4b is left. That is, the phase shifter shown in FIG. 14A can be depicted as FIG. 14b . If the small resistance 9 is ignored, the phase shifter shown in FIG. 14B can be depicted as FIG. 14C. Further, the line 14 shown in FIG. 14C can be replaced with two open stubs 15a and 15b as shown in FIG. 14D.
When the line 14 has an impedance Z1 and an angle θ1, each of the open stubs 15a and 15b has the impedance Z1 and an angle θ/2 (see Patent Document 5).
The magnitude of each of the inductors 4a and 4b varies depending on a desired shift amount. When a 45-degree phase shifter operating at 12 GHz is designed using a GaAs substrate having a dielectric constant of about 13 and a thickness of 50μ as a semiconductor substrate, the inductor 4a has an inductance of about 1.5 nH. When the inductor 4a is formed into a spiral structure, it is proved by simulation that the inductor 4a is substantially equivalent to a line of about 1 to 2 mm. In this case, each of the open stubs 15a and 15b has a length of about 0.5 to 1 mm. Because a wavelength λ at 12 GHz is about 7.5 mm on the GaAs substrate, it is apparent that each of the open stubs 15a and 15b having a length of λ/4 or smaller functions as a capacitance and has a capacitance of about 0.1 to 0.3 PF.
Accordingly, in the case of the circuit shown in FIG. 14D, a capacitance of about 0.3 PF is grounded in parallel with a signal line. This results in lowering the impedance. In other words, when the FET 5 connected in series with the signal line is in the on-state and the FET 7 connected in parallel with the signal line is in the off-state, the return loss is degraded and the passage loss increases.